CD54HC4017 Datasheet, PDF (6/14 Pages) Texas Instruments – High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

CD54HC4017, CD74HC4017
Test Circuits and Waveforms (Continued)
t_rC_L
CLOCK
INPUT
90%
10%
t_H(H)
t_fC_L
50%
t_H(L)
DATA
INPUT
t_SU(H)
t_SU(L)
OUTPUT
t_REM
V_CC
SET, RESET
OR PRESET
t_TLH
90%
t_PLH
50%
t_THL
90%
50%
10%
t_PHL
IC
C_L
50pF
V_CC
GND
V_CC
50%
GND
GND
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
Timing Diagrams
C_L
C_L
D
P
N
P
N
C_L
C_L
C_L
C_L
C
C_L
PN
C_L
P
N
C_L
R
FF DETAIL
FIGURE 4.
CLOCK
MASTER
RESET
CLOCK
ENABLE
“0” ₀
“1”
1
Q
“2”
2
“3”
3
“4”
4
Q
“5”
5
“6”
6
0
1
2
“7”
7
“8”
8
“9”
9
TERMINAL
COUNT
FIGURE 5.
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