CD54HC374_07 Datasheet, PDF (6/18 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns (Continued)
PARAMETER
Output Enable to Q
TEST
SYMBOL CONDITIONS V_CC (V) MIN
t_PZL, t_PZH C_L = 50pF
2
-
4.5
-
25^oC
TYP MAX
- 150
-
30
-40^oC TO
85^oC
MIN MAX
-
190
-
38
-55^oC TO
125^oC
MIN MAX UNITS
-
225 ns
-
45
ns
C_L = 15pF
5
-
12
-
-
-
-
-
ns
C_L = 50pF
6
-
-
26
-
33
-
38
ns
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
-
60
-
-
-
-
-
MHz
Output Transition Time
t_THL, t_TLH C_L = 50pF
2
-
-
60
-
75
-
90
ns
4.5
-
-
12
-
15
-
18
ns
6
-
-
10
-
13
-
15
ns
Input Capacitance
Three-State Output
Capacitance
C_I
C_L = 50pF
-
10
-
10
-
10
-
10
pF
C_O
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance C_PD
C_L = 15pF
5
(Notes 3, 4)
-
39
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
Clock to Output
t_PHL, t_PLH
C_L = 50pF
4.5
-
-
33
-
41
-
50
ns
C_L = 15pF
5
-
15
-
-
-
-
-
ns
Output Disable to Q
t_PLZ, t_PHZ C_L = 50pF
4.5
-
-
28
-
35
-
42
ns
C_L = 15pF
5
-
11
-
-
-
-
-
ns
Output Enable to Q
t_PZL, t_PZH C_L = 50pF
4.5
-
-
30
-
38
-
45
ns
C_L = 15pF
5
-
12
-
-
-
-
-
ns
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
-
60
-
-
-
-
-
MHz
Output Transition Time
t_TLH, t_THL C_L = 50pF
4.5
-
-
12
-
15
-
18
ns
Input Capacitance
C_I
C_L = 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
C_O
-
-
20
-
20
-
20
-
20
pF
Power Dissipation Capacitance C_PD
C_L = 15pF
5
(Notes 3, 4)
-
47
-
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = C_PD V_CC2 f_i + ∑ V_CC2 f_O C_L where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
6