CD54HC259_06 Datasheet, PDF (6/14 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Addressable Latch

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns (Continued)
PARAMETER
A to Q
TEST
SYMBOL CONDITIONS V_CC (V) MIN
t_PHL
C_L = 50pF
2
-
4.5
-
25^oC
TYP MAX
- 185
-
37
-40^oC TO
85^oC
MIN MAX
-
230
-
46
-55^oC TO
125^oC
MIN MAX UNITS
-
280 ns
-
56
ns
MR to Q
C_L = 15pF
5
C_L = 50pF
6
t_PHL, t_PLH C_L = 50pF
2
4.5
-
15
-
-
-
-
-
-
31
-
39
-
-
-
155
-
195
-
-
-
31
-
39
-
-
ns
48
ns
235 ns
47
ns
Output Transition Time
C_L = 15pF
5
-
13
-
-
-
-
-
ns
C_L = 50pF
6
-
-
26
-
33
-
40
ns
t_THL, t_TLH C_L = 50pF
2
-
-
75
-
95
-
110 ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Power Dissipation Capacitance C_PD
C_L = 15pF
5
(Notes 3, 4)
-
21
-
-
-
-
-
pF
Input Capacitance
HCT TYPES
C_I
C_L = 50pF
-
10
-
10
-
10
-
10
pF
Propagation Delay
D to Q
t_PHL, t_PLH
C_L = 50pF
4.5
-
-
39
-
49
-
59
ns
C_L = 15pF
5
-
16
-
-
-
-
-
ns
LE to Q
C_L = 50pF
4.5
-
-
38
-
48
-
57
ns
C_L = 15pF
5
-
16
-
-
-
-
-
ns
A to Q
C_L = 50pF
4.5
-
-
41
-
51
-
61
ns
C_L = 15pF
5
-
17
-
-
-
-
-
ns
MR to Q
C_L = 50pF
4.5
-
-
39
-
49
-
59
ns
C_L = 15pF
5
-
16
-
-
-
-
-
ns
Power Dissipation Capacitance C_PD
C_L = 15pF
5
(Notes 3, 4)
-
22
-
-
-
-
-
pF
Input Capacitance
C_I
C_L = 50pF
-
10
-
10
-
10
-
10
pF
Output Transition Time
t_THL, t_TLH C_L = 50pF
4.5
-
-
15
-
19
-
22
ns
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = C_PD V_CC2 f_i + ∑ C_L V_CC2 f_O where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance,
V_CC = Supply Voltage.
6