CD54HC245 Datasheet, PDF (6/7 Pages) Texas Instruments – High Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting

CD54HC245, CD54HCT245, CD74HC245, CD74HCT245
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT
DISABLE
50%
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
90%
10%
90%
6ns
10%
t_PZL
t_PZH
OUTPUTS
DISABLED
V_CC
GND
50%
50%
OUTPUTS
ENABLED
t_r
6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
t_f
2.7
1.3
6ns
0.3
t_PZL
3V
GND
10%
90%
t_PZH
OUTPUTS
DISABLED
1.3V
1.3V
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
R_L = 1kΩ
C_L
50pF
V_CC FOR t_PLZ AND t_PZL
GND FOR t_PHZ AND t_PZH
NOTE: Open drain waveforms t_PLZ and t_PZL are the same as those for three-state shown on the left. The test circuit is Output R_L = 1kΩ to
V_CC, C_L = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
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