CD54HC240_08 Datasheet, PDF (6/17 Pages) Texas Instruments – High-Speed CMOS Logic Octal Buffer/Line Drivers, Three-State

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDI-
TIONS
25^oC
V_CC
(V) MIN TYP MAX
-40^oC TO 85^oC
MIN TYP MAX
-55^oC TO 125^oC
MIN TYP MAX UNITS
Output Enable and Disable
Times
t_TLH, t_THL C_L = 50pF 4.5 -
- 30 -
- 38 -
- 45 ns
Output Transition Time
t_THL, t_TLH C_L = 50pF 4.5 -
- 12 -
Input Capacitance
C_I
C_L = 50pF - 10 - 10 -
Power Dissipation Capacitance
(Notes 3, 4)
C_PD
HCT240
-
5
- 40 -
-
- 15 -
- 10 -
-
-
-
- 18 ns
- 10 pF
-
-
pF
HCT241
-
5
- 38 -
-
-
-
-
-
-
pF
HCT244
-
5
- 40 -
-
-
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per channel.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT
DISABLE
50%
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
90%
10%
90%
6ns
10%
t_PZL
t_PZH
OUTPUTS
DISABLED
V_CC
GND
50%
50%
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
t_r
6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
t_f
2.7
1.3
6ns
0.3
t_PZL
3V
GND
10%
90%
t_PZH
OUTPUTS
DISABLED
1.3V
1.3V
OUTPUTS
ENABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
6