CD54HC166_08 Datasheet, PDF (6/16 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Output Transition Time
(Figure 3)
SYMBOL
t_TLH, t_THL
TEST
CONDITIONS
C_L = 50pF
V_CC (V)
2
4.5
25^oC
TYP MAX
-
75
-
15
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
95
110
ns
19
22
ns
6
-
13
16
19
ns
Propagation Delay
MR to Output
(Figure 3)
t_PHL
C_L = 50pF
2
-
160
200
4.5
-
32
40
6
-
27
34
240
ns
48
ns
41
ns
Input Capacitance
Power Dissipation
Capacitance
(Notes 3, 4)
C_I
-
-
-
10
10
C_PD
-
5
41
-
-
10
pF
-
pF
HCT TYPES
Propagation Delay,
Clock to Output
(Figure 4)
t_PLH, t_PHL C_L = 50pF
4.5
-
40
50
60
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
(Figure 4)
22
ns
Propagation Delay
t_PHL
C_L = 50pF
4.5
-
40
50
MR to Output (Figure 4)
60
ns
Input Capacitance
NOTES:
C_I
-
-
-
10
10
10
pF
3. C_PD is used to determine the dynamic power consumption, per gate.
4. P_{D =} C_PD V_CC2f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
Test Circuits and Waveforms
t_rC_L
CLOCK
90%
10%
t_fC_L
50%
10%
t_WL
t_WL
+
t_WH
=
I
f_CL
50%
50%
t_WH
V_CC
GND
t_rC_L = 6ns
CLOCK
2.7V
0.3V
t_fC_L = 6ns
t_WL
+
t_WH
=
I
fC_L
3V
1.3V
0.3V
1.3V
1.3V
GND
t_WL
t_WH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
6