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CD54HC112 Datasheet, PDF (6/13 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
◁
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Output Transition Time
tTLH, tTHL CL = 50pF
2
-
- 75
-
95
-
110
ns
CL = 50pF
4.5 -
-
15
-
19
-
22
ns
CL = 50pF
6
-
- 13
-
16
-
19
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX CL = 15pF
5
- 60 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
- 12 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
CP to Q, Q
tPLH, tPHL CL = 50pF
4.5 -
-
35
-
44
-
53
ns
CL = 15pF
5
- 14 -
-
-
-
-
ns
Propagation Delay,
S to Q, Q
tPLH, tPHL CL = 50pF
4.5 -
-
32
-
40
-
48
ns
CL = 15pF
5
- 13 -
-
-
-
-
ns
Propagation Delay,
R to Q, Q
tPLH, tPHL CL = 50pF
4.5 -
-
37
-
46
-
56
ns
CL = 15pF
5
- 14 -
-
-
-
-
ns
Output Transition Time
tTLH, tTHL CL = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
- 60 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 4, 5)
CPD
-
5
- 20 -
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD = CPD VCC2 fi + Σ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
6
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