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CD54HC107 Datasheet, PDF (6/11 Pages) Texas Instruments – Dual J-K Flip-Flop with Reset Negative-Edge Trigger
◁
CD54HC107, CD74HC107, CD74HCT107
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
- 31 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
CP to Q
tPLH, tPHL CL = 50pF 4.5 -
-
43
-
54
-
65
ns
CL = 15pF
5
- 18 -
-
-
-
-
ns
Propagation Delay,
CP to Q
tPLH, tPHL CL = 50pF 4.5 -
-
40
-
50
-
60
ns
CL = 15pF
5
- 17 -
-
-
-
-
ns
Propagation Delay,
R to Q, Q
tPLH, tPHL CL = 50pF 4.5 -
-
38
-
48
-
57
ns
CL = 15pF
5
- 16 -
-
-
-
-
ns
Output Transition Time
tTLH, tTHL CL = 50pF 4.5 -
-
15
-
19
-
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
CP Frequency
fMAX
CL = 15pF
5
- 56 -
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
- 30 -
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
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