CD54AC273 Datasheet, PDF (6/15 Pages) Texas Instruments – Octal D Flip-Flop with Reset

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case) (Continued)
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
Propagation Delay,
MR to Qn
SYMBOL
V_CC (V)
MIN
t_PLH, t_PHL
1.5
-
3.3
4.9
TYP
MAX
MIN
TYP
MAX UNITS
-
154
-
-
169
ns
-
17.2
4.7
-
18.9
ns
5
3.5
-
12.3
3.4
-
13.5
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
45
-
-
45
-
pF
ACT TYPES
Propagation Delay,
CP to Qn
t_PLH, t_PHL
5
3.5
(Note 10)
-
12.3
3.4
-
13.5
ns
Propagation Delay,
MR to Qn
t_PLH, t_PHL
5
3.5
-
12.3
3.4
-
13.5
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
45
-
-
45
-
pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CAACC_PD:TP:isPDu_D=s=eCdCPt_DPo_DVdVeCt_CCe_2Crm_2fiifn=_i e+_∑t_∑h(Ce(C_Ldy_LVnCVaCCm_2Cic_2fopf)_oo)w+eVr c_Co_Cns_∆uI_Cm_Cptwiohnepreerf_if=lipi-nfploupt.frequency, _{fo = output frequency, CL = output load capacitance,}
V_CC = supply voltage.
INPUT
LEVEL
CP
10%
Q
t_r
90%
V_S
t_W
t_f
V_S
10%
t_PHL
V_S
V_S
t_PLH
V_S
INPUT
LEVEL
MR
GND
INPUT
CP
(Q)
Q
V_S
V_S
t_W
t_PLH
V_S
t_REM
V_S
FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK
PULSE WIDTH
FIGURE 2. PREREQUISITE AND PROPAGATION DELAY
TIMES FOR MASTER RESET
6