CD54AC164_07 Datasheet, PDF (6/16 Pages) Texas Instruments – 8-Bit Serial-In/Parallel-Out Shift Register

CD54/74AC164, CD54/74ACT164
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case) (Continued)
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
Propagation Delay,
MR to Qn
SYMBOL
V_CC (V)
MIN
t_PLH, t_PHL
1.5
-
3.3
5
TYP
MAX
MIN
TYP
MAX UNITS
-
158
-
-
174
ns
-
17.7
4.9
-
19.5
ns
5
3.6
-
12.6
3.5
-
13.9
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
-
-
10
-
-
10
pF
-
150
-
-
150
-
pF
ACT TYPES
Propagation Delay, CP to Qn
t_PLH, t_PHL
5
3.8
(Note 10)
-
13.5
3.7
-
14.9
ns
Propagation Delay, MR to Qn
t_PLH, t_PHL
5
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 11)
4.1
-
14.4
4
-
15.8
ns
-
-
10
-
-
10
pF
-
150
-
-
150
-
pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C_PD is used to determine the dynamic power consumption per device.
P_D = C_PDV_CC2 f_i Σ (C_LV_CC2 f_o) + V_CC ∆I_CC, where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC =
supply voltage.
t_r
t_f
CP
90%
10%
ANY 90%
OUTPUT _10%
t_w
1/f_MAX
t_PLH t_PHL
t_TLH t_THL
INPUT
V_S
GND
V_S
FIGURE 1.
MR
ANY
INPUT
V_S
t_PHL
CP
t_w
V_S
t_REC
INPUT LEVEL
GND
INPUT LEVEL
V_S
GND
FIGURE 2.
DS2 (1)
DS1 (2)
CP
VALID
V_S
t_SU
t_H
V_S
t_SU
t_H
t_REC
V_S
FIGURE 3.
INPUT
LEVEL
GND
INPUT
LEVEL
GND
INPUT
LEVEL
GND
DS2 (1)
CP
V_S
t_SU
t_H
V_S
FIGURE 4.
INPUT LEVEL
GND
INPUT LEVEL
GND
6