BQ2058T Datasheet, PDF (6/18 Pages) Texas Instruments – Lithium Ion Pack Supervisor For 2-Cell Packs

bq2058T
CHG and DSG States
The CHG and DSG output truth table is shown below:
Condition
Normal operation
Overvoltage
Undervoltage
Overcurrent
Floating battery input
CTL = high
CHG pin
High
Z
High
High
Z
Z
DSG pin
High
High
Low
Low
Indeterminate
Low
The polarities of CHG and DSG are mask programmable
at Benchmarq. Push-pull vs. open-drain configuration is
also mask-configurable at Benchmarq. Please contact
Benchmarq for availability of these variations.
Pack Disable Input–CTL
The CTL pin is used to electrically disconnect the bat-
tery from the pack terminals through an externally sup-
plied signal. When CTL is taken high, CHG goes to the
high impedance state and DSG is driven low. Any load
on the pack terminals will be interpreted as an overcur-
rent condition by the bq2058T with the overcurrent de-
lay timer held in reset. When the CTL pin is driven low,
the overcurrent delay timer is allowed to start. If the
programmed delay (tOCD) is too short, the overcurrent
recovery circuit, if implemented, will be unable to cor-
rect the overcurrent situation prior to the delay time-
out. It is recommended that a delay time of greater than
10ms (COCD ≥ 0.01µF) be used if the CTL pin function
is to be utilized.
Important note: If CTL floats, it is internally
pulled high making both DSG and CHG inactive,
thus disabling the pack. If CTL is not used, it
should be tied to V_SS.
The polarity of CTL is mask-programmable at Bench-
marq. Please contact Benchmarq for other polarity op-
tions.
Protection Delay Timers
The delay time between the detection of an overcurrent,
overvoltage, or undervoltage condition and the deactiva-
tion of the CHG and/or DSG outputs is user-configurable
by the selection of capacitor values between VCC and OCD,
OVD, and UVD pins (respectively. See Table 2 below.
The fault condition must persist through the entire de-
lay period, or the bq2058T may not deactivate either
FET control output.
Figure 3 shows a step-by-step event cycle for the
bq2058T.
Table 2. Protection Delay Timers
Protection
Feature
Overcurrent
Overvoltage
Undervoltage
Delay
Period
tOCD
tOVD
tUVD
Capacitor from
VCC to:
OCD
OVD
UVD
Typical
Capacitor
0.010µF
0.100µF
0.100µF
Time
12ms
950ms
950ms
Tolerance
±40%
±40%
±40%
Notes: 1. The delay time versus capacitance can be approximated by the following equations:.
For tOCD:
t(s) ≈ 1.2 ∗ C(µf), where 0.001µF ≤ C ≤ 0.1µF
For tOVD, tUVD: t(s) ≈ 9.5 ∗ C(µf), where 0.01µF ≤ C ≤ 1µF
2. Overvoltage and undervoltage conditions are sampled by the bq2058T. The delay in Table 2 is in
addition to the time required for the bq2058T to detect the violation, which may vary from 0 to
120 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously
monitored and is subject to a delay of approximately 1.5ms.
July 1997
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