54AC16373_07 Datasheet, PDF (6/11 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

54AC16373, 74AC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS121B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
2 × VCC
S1
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
GND
LOAD CIRCUIT
Input
tw
50%
50%
VOLTAGE WAVEFORMS
VCC
0V
Timing Input
(see Note B)
tsu
Data Input
50%
th
50%
50%
VOLTAGE WAVEFORMS
VCC
0V
VCC
0V
Input
50%
50%
VCC
0V
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZH
50%
50%
tPLZ
50% VCC
tPHZ
20% VCC
50% VCC
80% VCC
VOLTAGE WAVEFORMS
VCC
0V
[ VCC
VOL
VOH
[0V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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