TRF2443_15_15 Datasheet, PDF (59/85 Pages) Texas Instruments – Integrated IF Transceiver for Broadband Wireless Applications

TRF2443
www.ti.com
SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012
REGISTER
5
NAME
Bit27 XDCOFF_CLK_0
Bit28 XDCOFF_CLK_1
Bit29 XDCOFF_CLK_2
Bit30 RSV
Bit31 PWD_XPICDCOFF
POWER-ON
VALUE
0
0
1
1
0
SUGGESTED
VALUE
DESCRIPTION
0
XPIC dc offset-loop clock-speed control
0
1
1
Reserved
0
Power down XPIC dc-offset loop (1 = disable)
EN_BB_AUTOCAL (bit5): When 1, the RX baseband dc-offset automatic calibration starts. At the end of the
calibration, the bit is reset to 0.
DCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC used in
the RX chain.
DCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the RX dc-offset correction-loop clock from the
clock divider.
EN_BB_CAL (bit17): When 1, the RX baseband dc-offset loop is enabled.
EN_XPIC_AUTOCAL (bit18): When 1, the XPIC baseband dc-offset automatic calibration starts. At the end of
the calibration, the bit is reset to 0.
XPICDCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC
used in the XPIC chain.
XDCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the XPIC dc-offset correction-loop clock from
the clock divider.
SPI3 Register 6
Register address
Bit0 Bit1 Bit2
IFVGA2 gain-range
control
Bit16 Bit17 Bit18
SPI address
Bit3 Bit4
IFVGA3 gain-range control
Bit5 Bit6 Bit7 Bit8 Bit9
IFVGA3 min. gain
Bit10 Bit11 Bit12 Bit13
IFVGA2 gain-
range control
Bit14 Bit15
IFVGA2 min. gain
Bit19 Bit20 Bit21 Bit22
IFVGA1 gain-range control
Bit23 Bit24 Bit25 Bit26 Bit27
IFVGA1 min. gain
Bit28 Bit29 Bit30 Bit31
REGISTER
6
NAME
Bit0
ADDR_0
Bit1
ADDR_1
Bit2
ADDR_2
Bit3
ADDR_3
Bit4
ADDR_4
Bit5
IFVGA3_RANGE_0
Bit6
IFVGA3_RANGE_1
Bit7
IFVGA3_RANGE_2
Bit8
IFVGA3_RANGE_3
Bit9
IFVGA3_RANGE_4
Bit10 IFVGA3_ MINGAIN_0
Bit11 IFVGA3_MINGAIN_1
Bit12 IFVGA3_MINGAIN_2
Bit13 IFVGA3_MINGAIN_3
POWER-ON
VALUE
0
1
1
1
1
0
0
1
1
1
0
1
0
0
SUGGESTED
VALUE
DESCRIPTION
0
Register address bits
1
1
1
SPI address bits
1
0
IFVGA3 gain-range control
1
0
1
0
0
IFVGA3 minimum-gain control
1
0
0
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