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TMS320VC5402A Datasheet, PDF (59/98 Pages) Texas Instruments – Fixed-Point Digital Signal Processor
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TMS320VC5402A
Fixed-Point Digital Signal Processor
SPRS015E – SEPTEMBER 2001 – REVISED JANUARY 2005
5.3.4 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.3.4.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or
four to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5-3.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left
unconnected.
Table 5-2 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and Divide-By-4 Clock Options
CLKMD1
0
1
1
CLKMD2
0
0
1
CLKMD3
0
1
1
Clock Mode
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled
Table 5-3 and Table 5-4 assume testing over recommended operating conditions and H = 0.5tc(CO)(see
Figure 5-3).
Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
MIN MAX UNIT
20
ns
4 ns
4 ns
4
ns
4
ns
Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
PARAMETER
MIN TYP MAX UNIT
tc(CO)
Cycle time, CLKOUT
6.25 (1)
(2)
ns
td(CIH–CO) Delay time, X2/CLKIN high to CLKOUT high/low
4
7 11
ns
tf(CO)
Fall time, CLKOUT
1
ns
tr(CO)
Rise time, CLKOUT
1
ns
tw(COL)
Pulse duration, CLKOUT low
H –3
H H + 3 ns
tw(COH)
Pulse duration, CLKOUT high
H–3
H H + 3 ns
(1) It is recommended that the PLL clocking option be used for maximum frequency operation.
(2) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Specifications
59
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