TMS370C742 Datasheet, PDF (58/69 Pages) Texas Instruments – CMOS EEPROM/EPROM Technologies on a Single Device

TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
ADC1 (continued)
The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the
sample time is user-defined such that high-impedance sources can be accommodated without penalty to
low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register
(ADCTL) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START)
of the ADCTL is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START
bits, signaling that a conversion has started and the analog signal can be removed.
analog timing requirements
MIN MAX UNIT
t_su(S) Setup time, analog input to sample command
0
ns
t_h(AN) Hold time, analog input from start of conversion
18t_c
ns
t_w(S) Pulse duration, sample time per kilohm of source impedance (see Note 14)
1
s/k
NOTE 14: The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time
of 1 s.
Analog Stable
Analog
In
Sample
Start
Convert
Start
t_su(S)
t_w(S)
t_h(AN)
Figure 23. Analog Timing
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