ADS62P45 Datasheet, PDF (58/67 Pages) Texas Instruments – Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs

ADS62P45, ADS62P44
ADS62P43, ADS62P42
REV1P0 SEP 2007
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Decimation filter equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit signed).
The filter equation is:
y(n)
=

1
2¹¹

•
(h0
•
x(n)
+
h1 •
x(n
-
1)
+
h2
•
x(n
-
2)
+
…
+
h11 •
x(n
-
11)
+
h11 •
x(n
-
12)
+
…
+
h1 •
x(n
-
22)
+
h0
•
x(n
-
23))
By setting the register bit <ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
y(n)
=

1
2¹¹

•
(h0
•
x(n)
+
h1 •
x(n
-
1)
+
h2
•
x(n
-
2)
+
…
+
h10
•
x(n
-
10)
+
h11 •
x(n
-
11)
+
h10
•
x(n
-
12)
+
…
+
h1 •
x(n
-
21)
+
h0
•
x(n
-
22)
In the above equations,
h0, h1 …h11 are 12 bit signed representation of the coefficients,
x(n) is the input data sequence to the filter &
y(n) is the filter output sequence.
Pre-defined coefficients
The in-built filter types (low pass, high pass & band pass) use pre-defined coefficients. The frequency response of the in-built
filters is shown in Figure 28 & Figure 29.
TBD
Figure 28 Decimate by 2 filter response
TBD
Figure 29 Decimate by 4 filter response
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the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
58
discontinue these products without notice.
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