TLV320AIC3111_101 Datasheet, PDF (57/154 Pages) Texas Instruments – Low-Power Audio Codec With Embedded miniDSP and Stereo Class-D Speaker Amplifier

TLV320AIC3111
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SLAS644B – JULY 2009 – REVISED OCTOBER 2009
This feature is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections due
to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for
glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is
provided. This can be programmed via page 0 / register 67, bits D4–D2. For improved button-press
detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register 67,
bits D1–D0.
The TLV320AIC3111 also provides feedback to the user through register-readable flags as well as an
interrupt on the I/O pins when a button press or a headset insertion/removal event is detected. The value
in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion.
Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected.
Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is
detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires
polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320AIC3111 also
provides an interrupt feature, whereby events can trigger the INT1 and/or INT2 interrupts. These interrupt
events can be routed to one of the digital output pins. See Section 5.6.6 for details.
The TLV320AIC3111 not only detects a headset insertion event, but also is able to distinguish between
the different headsets inserted, such as stereo headphones or cellular headphones. After the
headset-detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of
headset inserted.
Register
Page 0 / register 67, bit D1
Page 0 / register 67, bits D4–D2
Page 0 / register 67, bits D1–D0
Page 0 / register 44, bit D5
Page 0 / register 44, bit D4
Page 0/ register 46, bit D5
Page 0 / register 46, bit D4
Page 0 / register 67, bits D6–D5
Table 5-34. Headset-Detection Block Registers
Description
Headset-detection enable/disable
Debounce programmability for headset detection
Debounce programmability for button press
Sticky flag for button-press event
Sticky flag for headset-insertion or -removal event
Status flag for button-press event
Status flag for headset insertion and removal
Flags for type of headset detected
The headset detection block requires AVDD to be powered. The headset detection feature in the
TLV320AIC3111 is achieved with very low power overhead, requiring less than 20 μA of additional current
from the AVDD supply.
5.6.6 Interrupts
Some specific events in the TLV320AIC3111 which may require host processor intervention, can be used
to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The
TLV320AIC3111 has two defined interrupts, INT1 and INT2, that can be configured by programming
page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be
triggered by one or many events, such as:
• Headset detection
• Button press
• DAC DRC signal exceeding threshold
• Noise detected by AGC
• Overcurrent condition in headphone drivers/speaker drivers
• Data overflow in ADC and DAC processing blocks and filters
• DC measurement data available
Copyright © 2009, Texas Instruments Incorporated
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