PCI1520GHK Datasheet, PDF (54/139 Pages) Texas Instruments – PC Card Controllers

BIT NAME
SMIROUTE
SMISTAT
SMIENB
Table 3−12. SMI Control
FUNCTION
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing register (PCI offset 8Ch, see Section 4.30).
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1520, various features are designed into the
device to allow implementation of popular power-saving techniques. These features and techniques are discussed
in this section.
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI1520 requires 2.5-V core voltage. The core power can be supplied by the PCI1520 itself using the internal
LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal.
Table 3−13 lists the requirements for both the internal core power supply and the external core power supply.
SUPPLY
Internal
External
Table 3−13. Requirements for Internal/External 2.5-V Core Power Supply
VCC VR_EN
3.3 V GND
VR_PORT
2.5-V output
NOTE
Internal 2.5-V LDO-VR is enabled. A 1.0 µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
3.3 V VCC
2.5-V input Internal 2.5-V LDO-VR is disabled. An external 2.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1 µF bypass capacitor on the VR_PORT terminal is required.
3.8.2 Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1520. CLKRUN
signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not
always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the PCI Mobile Design Guide.
The PCI1520 does not permit the central resource to stop the PCI clock under any of the following conditions:
• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
• The 16-bit PC Card- resource manager is busy.
• The PCI1520 CardBus master state machine is busy. A cycle may be in progress on CardBus.
• The PCI1520 master is busy. There may be posted data from CardBus to PCI in the PCI1520.
• Interrupts are pending.
• The CardBus CCLK for either socket has not been stopped by the PCI1520 CCLKRUN manager.
3−19