AFE5804_1 Datasheet, PDF (52/61 Pages) Texas Instruments – FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.89nV/√Hz, 12-Bit, 40MSPS, 101mW/Channel

AFE5804
SBOS442B – JUNE 2008 – REVISED NOVEMBER 2008.................................................................................................................................................. www.ti.com
VCA—GAIN CONTROL
The attenuator (VCA) for each of the eight channels
of the AFE5804 is controlled by a single-ended
control signal input, the V_CNTL pin. The control voltage
range spans from 0V to 1.2V, referenced to ground.
This control voltage varies the attenuation of the VCA
based on its linear-in-dB characteristic with its
maximum attenuation (minimum gain) at V_CNTL = 0V,
and minimum attenuation (maximum gain) at V_CNTL =
1.2V. Table 18 shows the nominal gains for each of
the four PGA gain settings. The total gain range is
typically 46dB and remains constant independent of
the PGA selected; the Max Gain column reflects the
absolute gain of the full signal path comprised of the
fixed LNA gain of 20dB and the programmable PGA
gain.
Table 18. Nominal Gain Control Ranges for Each
of the Four PGA Gain Settings
PGA GAIN
20dB
25dB
27dB
30dB
MIN GAIN
AT V_CNTL = 0V
–5.5dB
–1.0dB
1.0dB
3.0dB
MAX GAIN AT
V_CNTL = 1.2V
40.5dB
45.0dB
47.0dB
49.0dB
As previously discussed, the VCA architecture uses
eight attenuator segments that are equally spaced in
order to approximate the linear-in-dB gain-control
slope. This approximation results in a monotonic
slope; gain ripple is typically less than ±0.5dB.
The AFE5804 gain-control input has a –3dB
bandwidth of approximately 1.5MHz. This wide
bandwidth, although useful in many applications, can
allow high-frequency noise to modulate the gain
control input. In practice, this modulation can easily
be avoided by additional external filtering (R_F and C_F)
of the control input, as Figure 101 shows. Stepping
the control voltage from 0V to 1.2V, the gain control
response time is typically less than 500ns to settle
within 10% of the final signal level of a 1V_PP
(–6dBFS) output.
The control voltage input (VCNTL pin) represents a
high-impedance input. Multiple AFE5804 devices can
be connected in parallel with no significant loading
effects using the VCNTL pin of each device. Note that
when the V_CNTL pin is left unconnected, it floats up to
a potential of about +3.7V. For any voltage level
above 1.2V and up to 5.0V, the VCA continues to
operate at its minimum attenuation level; however, it
is recommended to limit the voltage to approximately
1.5V or less.
When the AFE5804 operates in CW mode, the
attenuator stage remains connected to the LNA
outputs. Therefore, it is recommended to set the
V_CNTL voltage to +1.2V in order to minimize the
internal loading of the LNA outputs. Small
improvements in reduced power dissipation and
improved distortion performance may also be
realized.
AFE5804
Attenuator
R_S
LNA
R_S
To
PGA
VCNTL
R_F
C_F
Figure 101. External Filtering of the V_CNTL Input
CW DOPPLER PROCESSING
The AFE5804 integrates many of the elements
necessary to allow for the implementation of a CW
doppler processing circuit, such as a V/I converter for
each channel and a cross-point switch matrix with an
8-input into 10-output (8×10) configuration.
In order to switch the AFE5804 from the default TGC
mode operation into CW mode, bit D5 of the control
register must be updated to low ('0'). This setting also
enables access to all other registers that determine
the switch matrix configuration (see the Input Register
Bit Map tables). In order to process CW signals, the
LNA internally feeds into a differential V/I amplifier
stage. The transconductance of the V/I amplifier is
typically 13.5mA/V with a 100mV_PP input signal. For
proper operation, the CW outputs must be connected
to an external bias voltage of +2.5V. Each CW output
is designed to sink a small dc current of 0.9mA, and
can deliver a signal current up to 2.9mA_PP.
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