TPS658621A_1 Datasheet, PDF (51/107 Pages) Texas Instruments – Advanced Power Management Unit

TPS658621A
www.ti.com
SLVSA58 – DECEMBER 2009
When 1
Table 3-15. Sequencer Control, LDO5/LDO9 Enable (continued)
ON
ON
ENABLED
5ms
SET SLEEP
FORCE
TRANSITION
TO NORMAL
STATE
REBOOT
REQUEST
SLEEP STATE: When the SLEEP state is set all supplies are set to OFF mode (with exception of
RTC_LDO) and the NOPOWER output is pulled low. A few internal blocks are still active, enabling
detection of system status changes that trigger the SLEEP state exit.
All I²C engines are reset and all RAM registers are reset to their default condition when the SLEEP state
is set. The RAM bits that have a default set via the non-volatile memory will keep the value they had
before the SLEEP state was set.
The SLEEP state ends when one of the following sequences is executed:
A. If SLEEP was set by thermal fault: The SLEEP state will end only when all external input supplies and
battery pack are removed and an UVLO condition is detected by the TPS658621A, setting the POWER
UP state.
B. If SLEEP was not set by thermal fault: The SLEEP state will end when a hardware sleep exit request is
detected at RESUME pin
EXITING THE SLEEP STATE: The figure below shows the timing relationship needed on the RESUME
pin to exit the sleep mode. This applies for all cases where the sleep mode entry was triggered by any
event other than a thermal fault.
RESUME PIN
T_RESUME(H)
T_RESUME(L)
T_RESUME(H)
TPS6586x
MODE
NORMAL MODE
ENTER/EXIT
SLEEP
SLEEP MODE
SET SLEEP
NORMAL MODE
EXIT SLEEP
Figure 3-12. Entering and Exiting Sleep Mode Resume
REBOOT REQUEST: The REBOOT REQUEST state is entered from the NORMAL state. It can be set via
software (SOFT_RST set to 1, register 0x14 Bit B0) or by a V_IL level detection at HOTRST pin. When the
reboot request state is set an internal timer T_WAIT (10ms typ) is started, and the NOPOWER pin is pulled
to ground. The reboot request ends when t > T_WAIT. The REBOOT REQUEST will transition the device
state machine to the HARD REBOOT state. The REBOOT REQUEST is set if the HOTRST low pulse
width is greater than 10μsec (typ).
The status bit COMPDET=1 (register STAT2, address 0xBA) when the NORMAL state is entered after a
reboot cycle triggered by the HOTRST pin. The status bit COMPDET=0 when the NORMAL state is
entered, after a power-up, sleep cycle or software triggered reboot cycle.
The bit COMPDET is reset to 0 when bit SPARECC0=1, in register SPARE2 (address 0xCC). After
resetting the COMPDET bit the host needs to set SPARECC0=0 to enable detection of another reboot
cycle set via the HOTRST pin.
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