TMS320VC5407 Datasheet, PDF (50/110 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Functional Overview
Peripheral
Bus
Data
Bus
Buffer
8
S
e
l
e
c
8
t
Receiver
Buffer
Register
Line
Control
Register
Receiver
FIFO
Receiver
Shift
Register
Receiver
Timing and
Control
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Line
Status
Register
Transmitter
Holding
Register
Transmitter
S
FIFO
e
l
8
e
c
t
Transmitter
Timing and
Control
8 ^Transmitter
Shift
Register
Modem
Control
Register
Interrupt
Enable
Register
8 ^Interrupt
Control
Logic
Control
Logic
Interrupt
Identification
8
Register
FIFO
Control
Register
Figure 3−22. UART Functional Block Diagram
RX
TX
INTRPT
(To CPU)
50 SPRS007D
November 2001 − Revised April 2004