TLV320DAC3101_15 Datasheet, PDF (50/100 Pages) Texas Instruments – Low-Power Stereo Audio DAC With Audio Processing and Stereo Class-D Speaker Amplifier

TLV320DAC3101
SLAS666A – JANUARY 2010 – REVISED MAY 2012
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# 5. Power up DAC
# (a) Set register page to 0
#
w 30 00 00
#
# (b) Power up DAC channels and set digital gain
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# Powerup DAC left and right channels (soft step enabled)
w 30 3F D4
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# DAC Left gain = -22 dB
w 30 41 D4
# DAC Right gain = -22 dB
w 30 42 D4
#
# (c) Unmute digital volume control
#
# Unmute DAC left and right channels
w 30 40 00
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5.6 Clock Generation and PLL
The TLV320DAC3101 supports a wide range of options for generating clocks for the DAC section as well
as interface and other control blocks as shown in Figure 5-20. The clocks for the DAC require a source
reference clock. This clock can be provided on variety of device pins, such as the MCLK, BCLK, or GPIO1
pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value
on page 0 / register 4, bits D1–D0. CODEC_CLKIN can then be routed through highly-flexible clock
dividers shown in Figure 5-20 to generate the various clocks required for the DAC. In the event that the
desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the
TLV320DAC3101 also provides the option of using the on-chip PLL which supports a wide range of
fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the
TLV320DAC3101 provides several programmable clock dividers to help achieve a variety of sampling
rates for the DAC.
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APPLICATION INFORMATION
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