TLV320ADC3101 Datasheet, PDF (50/84 Pages) Texas Instruments – Low Power Stereo ADC for Wireless Handsets and Portable Audio

TLV320ADC3101
SLAS553 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com
Bit
D7 ⁽¹⁾
D6 ⁽¹⁾
D5 ⁽²⁾
D4
D3 ⁽¹⁾
D2 ⁽¹⁾
D1 ⁽²⁾
D0
Reset
Value
0
0
0
0
0
0
0
0
Page 0/Register 36: ADC Flag Register
Values Description
0
1
0
1
0
1
All values
0
1
0
1
0
1
All values
Left ADC PGA , Applied Gain not = Programmed Gain
Left ADC PGA , Applied Gain = Programmed Gain
Left ADC Powered Down
Left ADC Powered Up
Left AGC not Saturated
Left AGC Applied Gain = Maximum Applicable Gain by Left AGC
Reserved don't write any value other than reset value.
Right ADC PGA , Applied Gain not = Programmed Gain
Right ADC PGA , Applied Gain = Programmed Gain
Right ADC Powered Down
Right ADC Powered Up
Right AGC not Saturated
Right AGC Applied Gain = Maximum Applicable Gain by Right AGC
Reserved don't write any value other than reset value.
(1) Read Only Bits…Writing any value to this will not be get used anywhere.
(2) Sticky Flag BIts....These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger
occurs freshly again.
Bit
D7–D0
Reset
Value
0
Page 0/Register 37: Data Slot Offset Programmability 2
Values Description
0
Offset = 0BCLK's. Offset is measured with respect to the end of the first channel⁽¹⁾
1
Offset = 1BCLK's
2
Offset = 2BCLK's
254
Offset = 254BCLK's
255
Offset = 255BCLK's
(1) Usage controlled by Page 0/Register 38 (D0) time_slot_mode_enable
Bit
D7–D5
D4
D3–D2
D1
D0
Reset
Value
0
0
0
1
0
Page 0/Register 38: I2S TDM Control Register
Values Description
All values
0
1
0
1
2
3
0
1
0
1
Reserved don't write any value other than reset value.
Channel Swap Disabled.
Channel Swap Enabled.
Both left and right channels enabled
Left channel enabled
Right channel enabled
Both left and right channels disabled
early_3-state disabled
early_3-state enabled
time_slot_mode disabled (Both Channels offset controlled by Page 0/Register 28)
time_slot_mode enabled (Channel 1 offset controlled by Page 0/Register 28 and Channel 2
offset controlled by Page 0/Register 37)
50
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :TLV320ADC3101