TAS5508C Datasheet, PDF (50/107 Pages) Texas Instruments – 8-Channel Digital Audio PWM Processor

TAS5508C
SLES257 – SEPTEMBER 2010
Table 3-8. Volume Ramp Rates in ms
NUMBER OF STEPS
512
1024
2048
SAMPLE RATE (kHz)
44.1, 88.2, 176.4
32, 48, 96, 192
46.44 ms
42.67 ms
92.88 ms
85.33 ms
185.76 ms
170.67 ms
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3.3.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation
is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
For negative signals, the PWM modulations fall below 50% toward 0%.
However, there is a limit to the maximum modulation possible. During the offtime period, the power stage
connected to the TAS5508C output needs to get ready for the next ontime period. The maximum possible
modulation is then set by the power stage requirements. All Texas Instruments power stages need
maximum modulation to be 97.7%. This is also the default setting of the TAS5508C. Default settings can
be changed in the modulation index register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
3.3.8 Interchannel Delay
An 8-bit value can be programmed into each of the eight PWM interchannel delay registers to add a delay
per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock,
DCLK. The default values are shown in Table 3-9.
Table 3-9. Interchannel Delay Default Values
I²C SUBADDRESS
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
CHANNEL
1
2
3
4
5
6
7
8
INTERCHANNEL DELAY DEFAULT (DCLK PERIODS)
–24
0
–16
16
–24
8
–8
24
This delay is generated in the PWM and can be changed at any time through the serial-control interface
I²C registers 0x1B–0x22. The absolute offset for channel 1 is set in I²C subaddress 0x23.
NOTE
If used correctly, setting the PWM channel delay can optimize the performance of a
PurePath Digital™ amplifier system . The setting is based on both the type of back-end
power device that is used and the layout. These values are set during initialization using the
I²C serial interface. Unless otherwise noted, use the default values given in Table 3-9.
3.4 Master Clock and Serial Data Rate Controls
The TAS5508C functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5508C to detect MCLK and the data rate automatically.
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TAS5508C Controls and Status
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