DAC34SH84_15 Datasheet, PDF (50/93 Pages) Texas Instruments – DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

DAC34SH84
SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015
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Device Functional Modes (continued)
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into multiple
DAC devices can experience different delays due to variations in the digital source output paths or board level
wiring. These different delays can be effectively absorbed by the DAC34SH84 FIFO so that all outputs are phase
aligned correctly.
DACCLKP/N
FPGA
LVPECL Outputs
OSTRP/N
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
Delay 1
DATACLKP/N
DAC34SH84 DAC1
Clock Generator
LVPECL Outputs
PLL/
DLL
Variable delays due to variations in the FPGA(s) output
DAB[15:0]P/N ^{paths or board level wiring or temperature/voltage deltas}
DCD[15:0]P/N
ISTRP/N
Delay 2
DATACLKP/N
OSTRP/N
DAC34SH84 DAC2
DACCLKP/N
Outputs are
Phase Aligned
Figure 84. Synchronization System in Dual Sync Sources Mode With PLL Bypassed
B0454-04
For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR
signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock
generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of
the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the
DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.
Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from
device to device with the lowest skew possible as this will affect the synchronization process. In order to
minimize the skew across devices it is recommended to use the same clock distribution device to provide the
DACCLK and OSTR signals to all the DAC devices in the system.
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