UCD9224_1 Datasheet, PDF (5/36 Pages) Texas Instruments – Digital PWM System Controller

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UCD9224
SLVSA35 – JANUARY 2010
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
PARAMETER
TEST CONDITIONS
t_FLT
Time to disable DPWM output based on corresponding
active FLT pin
High level on FLT pin
Time to disable the first DPWM output based on internal Step change in CS voltage from 0V to
analog comparator fault
2.5V
t_CLF
Time to disable all remaining DPWM and SRE outputs
configured for the voltage rail after an internal analog
comparator fault
Step change in CS voltage from 0V to
2.5V
MAX
15 + 3 ×
NumPhases
4
10 + 3 ×
NumPhases
UNIT
µs
Switch
Cycles
µs
PMBUS/SMBUS/I2C
The timing characteristics and timing diagram for the communications interface that supports I²C, SMBus and
PMBus are shown below.
I²C/SMBus/PMBus TIMING CHARACTERISTICS
T_A = –40°C to 125°C, 3V < V₃₃ < 3.6V, typical values at T_A = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f_SMB
f_I2C
t_(BUF)
t_(HD:STA)
t_(SU:STA)
t_(SU:STO)
t_(HD:DAT)
t_(SU:DAT)
t_(TIMEOUT)
t_(LOW)
t_(HIGH)
t_(LOW:SEXT)
t_FALL
t_RISE
SMBus/PMBus operating frequency
I²C operating frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Data hold time
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Clock/data fall time
Clock/data rise time
Slave mode; SMBC 50% duty cycle
Slave mode; SCL 50% duty cycle
Receive mode
See ⁽¹⁾
See ⁽²⁾
See ⁽³⁾
See ⁽⁴⁾
See ⁽⁵⁾
10
10
4.7
0.26
0.26
0.26
0
50
0.5
0.26
1000 kHz
1000 kHz
µs
µs
µs
µs
ns
ns
35 ms
µs
50 µs
25 ms
120 ns
120 ns
(1) The UCD9224 times out when any clock low exceeds t(TIMEOUT).
(2) t_(HIGH), max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9224 that is
in progress.
(3) t_(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Rise time t_RISE = V_ILMAX – 0.15) to (V_IHMIN + 0.15)
(5) Fall time t_FALL = 0.9 V₃₃ to (V_ILMAX – 0.15)
Copyright © 2010, Texas Instruments Incorporated
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