TPS54494_15 Datasheet, PDF (5/30 Pages) Texas Instruments – 4A/2A Dual Channel Synchronous Step-Down Switcher with Integrated FET

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HTSSOP PACKAGE
(TOP VIEW)
DEVICE INFORMATION
TPS54494
SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013
RSA PACKAGE
(TOP VIEW)
1 _VIN1
2 _{VBST 1}
3 _SW1
4 _PGND1
5 EN1
TPS54494
HTSSOP 16
VIN2 ¹⁶
VBST2 ¹⁵
SW 2 ¹⁴
PGND 2 ¹³
EN2 ¹²
16
15
14
13
VBST2 ¹
12 _VFB2
VIN2 ²
VIN1 ³
PowerPAD
11 _VREG5
10 _GND
6 PG1
7 VFB1
(PowerPAD)
PG2 ¹¹
VFB2 ¹⁰
VBST1 ⁴
9 _VFB1
5
6
7
8
8 GND
VREG5 9
NAME
VIN1
VIN2
VBST1,
VBST2
SW1
SW2
PGND1
PGND2
EN1
EN2
PG1
PG2
VFB1
VFB2
GND
PIN
PWP
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
VREG5
Exposed Thermal
Pad
9
Back side
RSA
3
2
4
1
5
16
6
15
7
14
8
13
9
12
10
11
Back side
PIN FUNCTIONS⁽¹⁾
I/O
DESCRIPTION
I Power inputs and connects to both high side NFET drains.
I ^{Supply Input for 5.5V linear regulator.}
I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic
I
capacitor between VBSTx and SWx pins. An internal diode is connected
between VREG5 and VBSTx
I/O _{Switch node connections for both the high-side NFETs and low–side NFETs.}
I/O ^{Input of current comparator.}
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
I/O
I
Enable. Pull High to enable according converter.
I
O _{Open drain power good outputs. Low indicates the corresponding output}
O ^{voltage is out of regulation.}
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
I
I/O Signal GND. Connect sensitive SSx and VFBx returns to GND at a single
point.
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic
capacitor of at least 1 µF. VREG5 is active when ENx is high.
I/O Thermal pad of the package. Must be soldered to achieve appropriate
dissipation. Must be connected to GND.
(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
Copyright © 2012–2013, Texas Instruments Incorporated
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