TPS54310-EP Datasheet, PDF (5/21 Pages) Texas Instruments – 3-V TO 6-V INPUT, 3-A OUTPUT,SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs(SWIFT™)

TPS54310-EP
www.ti.com ..................................................................................................................................................................................................... SLVS818 – APRIL 2008
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
AGND
1
VSENSE
2
COMP
3
PWRGD
4
BOOT
5
PH
6
PH
7
PH
8
PH
9
PH
10
20
RT
19
SYNC
18
SS/ENA
17
VBIAS
16
VIN
15
VIN
14
VIN
13
PGND
12
PGND
11
PGND
TERMINAL
NAME
NO.
AGND
1
BOOT
COMP
PGND
PH
PWRGD
RT
SS/ENA
5
3
11–13
6–10
4
20
18
SYNC
19
VBIAS
VIN
VSENSE
17
14–16
2
TERMINAL FUNCTIONS
DESCRIPTION
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE ≥ 90% V_ref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f_s.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1 µF to 1.0 µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): TPS54310-EP