TLV5617AIDR Datasheet, PDF (5/20 Pages) Texas Instruments – 2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOGnull

TLV5617A
2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS234F – JULY 1999 – REVISED JULY 2002
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER
IIH High-level digital input current
IIL
Low-level digital input current
Ci
Input capacitance
TEST CONDITIONS
VI = VDD
VI = 0 V
MIN TYP MAX UNIT
1 µA
–1
µA
8
pF
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ts(FS) Output settling time, full scale
RL = 10 kΩ,
CL = 100 pF, See Note 11
Fast
Slow
1
3
µs
3
10
ts(CC) Output settling time, code to code
RL = 10 kΩ,
CL = 100 pF, See Note 12
Fast
Slow
1
2
µs
SR
Slew rate
RL = 10 kΩ,
CL = 100 pF, See Note 13
Fast
Slow
3
0.5
V/µs
SNR
Glitch energy
Signal-to-noise ratio
DIN = 0 to 1, FCLK = 100 kHz, CS = VDD
5
nV–s
68
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion
fs = 102 kSPS, fout = 1 kHz, RL = 10 kΩ,
CL = 100 pF
65
dB
–62
SFDR Spurious free dynamic range
64
NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDC and 0xFDC to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
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