TLC7528C_15 Datasheet, PDF (5/28 Pages) Texas Instruments – DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS

TLC7528C, TLC7528E, TLC7528I
DUAL 8ĆBIT MULTIPLYING
DIGITALĆTOĆANALOG CONVERTERS
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
operating characteristics over recommended operating free-air temperature range,
V_refA = V_refB = 10V, V_OA and V_OB at 0V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5V
MIN TYP MAX
VDD = 15V
MIN TYP MAX
UNIT
Linearity error
± 1/2
± 1/2 LSB
Settling time (to 1/2LSB)
See Note 1
100
100
ns
Gain error
See Note 2
2.5
2.5 LSB
AC feedthrough
REFA to OUTA
See Note 3
REFB to OUTB
− 65
− 65
dB
− 65
− 65
Temperature coefficient of gain
See Note 4
0.007
0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
See Note 5
80
80
ns
Channel-to-channel ^{REFA to OUTB See Note 6}
isolation
REFB to OUTA See Note 7
77
77
dB
77
77
Measured for code transition from
Digital-to-analog glitch impulse area
00000000 to 11111111,
160
TA = +25°C
440
nV−s
Digital crosstalk
Measured for code transition from
00000000 to 11111111,
30
TA = +25°C
60
nV−s
Harmonic distortion
Vi = 6V, f = 1kHz, TA = +25°C
− 85
− 85
dB
NOTES:
1. OUTA, OUTB load = 100Ω, Cext = 13pF; WR and CS at 0V; DB0−DB7 at 0V to VDD or VDD to 0V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref − 1LSB.
3. Vref = 20V peak-to-peak, 100kHz sine wave; DAC data latches loaded with 00000000.
4. Temperature coefficient of gain measured from 0°C to +25°C or from +25°C to +70°C.
5. VrefA = VrefB = 10V; OUTA/OUTB load = 100Ω, Cext = 13pF; WR and CS at 0V; DB0−DB7 at 0V to VDD or VDD to 0V.
6. Both DAC latches loaded with 11111111; VrefA = 20V peak-to-peak, 100kHz sine wave; VrefB = 0; TA = +25°C.
7. Both DAC latches loaded with 11111111; VrefB = 20V peak-to-peak, 100kHz sine wave; VrefA = 0; TA = +25°C.
PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying DACs, DACA and DACB. Each DAC consists of an
inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between
DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state.
Most applications require only the addition of an external operational amplifier and voltage reference. A
simplified DAC circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (I_Ikg) flows across internal junctions, and as with most semiconductor devices,
doubles every 10°C. C_o is due to the parallel combination of the NMOS switches and has a value that depends
on the number of switches connected to the output. The range of C_o is 50pF to 120pF maximum. The equivalent
output resistance (r_o) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,
responds to the activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled regardless of the state of the WR signal.
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