TAS5548 Datasheet, PDF (5/120 Pages) Texas Instruments – 8-Channel HD Compatible Audio Processor with ASRC and PWM Output

TAS5548
www.ti.com
SLES270 – NOVEMBER 2012
2.1.2 Terminal Descriptions
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
5-V
TOLERANT
AVDD_PWM
50
P
AVSS
AVSS_PWM
BKND_ERR
DVDD1
DVDD2
DVSS1
DVSS2
HP_SEL
LRCLK
XTALI
MUTE
XTALO
PDN
PLL_FLTM
PLL_FLTP
PSVC/MCLKO
PWM_HPM_L
PWM_HPM_R
PWM_HPP_L
PWM_HPP_R
PWM_M_1
PWM_M_2
PWM_M_3
PWM_M_4
PWM_M_5
PWM_M_6
PWM_M_7
PWM_M_8
PWM_P_1
PWM_P_2
PWM_P_3
PWM_P_4
PWM_P_5
PWM_P_6
PWM_P_7
PWM_P_8
5
P
51
P
34
DI
35
P
14
P
36
P
13
P
17
DI
22
DI
11
DI
19
DI
12
DO
18
DI
6
AIO
7
AIO
33
DO
1
DO
3
DO
2
DO
4
DO
38
DO
40
DO
42
DO
44
DO
53
DO
55
DO
46
DO
48
DO
39
DO
41
DO
43
DO
45
DO
54
DO
56
DO
47
DO
49
DO
5V
5V
1.8 V
5V
5V
TERMINATION ⁽²⁾
DESCRIPTION
Pullup ⁽²⁾
Pullup ⁽²⁾
Pulldown ⁽²⁾
Pullup ⁽²⁾
Pullup ⁽²⁾
3.3-V analog power supply for PWM. This terminal can be connected to the
same power source used to drive power terminal DVDD; but to achieve low PLL
jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR
capacitor.
Analog ground
Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply
for optimized performance.
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to I2C parameters, with all H-
bridge drive signals going to a hard-mute state (Non PWM Switching).
3.3-V digital power supply. (It is recommended that decoupling capacitors of
0.1 μF and 10 μF be mounted close to this pin).
3.3-V digital power supply for PWM. (It is recommended that decoupling
capacitors of 0.1 μF and 10 μF be mounted close to this pin).
Digital ground 1
Digital ground 2
Headphone/speaker selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
Serial-audio data left/right clock (sampling-rate clock)
XTAL input. Connect to external 12.288 MHz XTAL
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
XTAL input. Connect to external 12.288 MHz XTAL
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The I2C parameters are preserved through a
power-down cycle, as long as RESET is not active.
PLL negative filter.
PLL positive filter.
Power-supply volume control PWM output or MCKO for external ADC (SDIN5
Source)
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 5 output (lineout L) (differential –)
PWM 6 output (lineout R) (differential –)
PWM 7 output (differential –)
PWM 8 output (differential –)
PWM 1 output (differential +)
PWM 2 output (differential +)
PWM 3 output (differential +)
PWM 4 output (differential +)
PWM 5 output (lineout L) (differential +)
PWM 6 output (lineout R) (differential +)
PWM 7 output (differential +)
PWM 8 output (differential +)
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic-1 input; pulldowns → logic-0 input). Devices that drive
inputs with pullups must be able to sink 20 μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 μA while maintaining a logic-1 drive level.
Copyright © 2012, Texas Instruments Incorporated
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