SN75LVDS86 Datasheet, PDF (5/14 Pages) Texas Instruments – FLATLINKE RECEIVER

SN75LVDS86
FLATLINK™ RECEIVER
SLLS268C – MARCH 1997 – REVISED MAY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
VIT+
VIT–
Positive-going differential input threshold voltage
Negative-going differential input threshold voltage‡
–100
100 mV
mV
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 4 mA
2.4
IOL = 4 mA
Disabled,
All inputs open
V
0.4 V
280 µA
Enabled,
AnP = 1 V,
AnM = 1.4 V, tc = 15.38 ns
58
72 mA
ICC
Quiescent current (average)
Enabled,
CL = 8 pF,
Grayscale pattern (see Figure 4),
tc = 15.38 ns
69
mA
Enabled,
CL = 8 pF,
Worst-case pattern (see Figure 5)
tc = 15.38 ns
94
mA
IIH
High-level input current (SHTDN)
VIH = VCC
±20 µA
IIL
Low-level input current (SHTDN)
VIL = 0
±20 µA
II
Input current (LVDS input terminals A and CLKIN)
0 ≤ VI ≤ 2.4 V
±20 µA
IOZ
High-impedance output current
VO = 0 or VCC
±10 µA
† _{All typical values are at VCC = 3.3 V, TA = 25°C.}
‡ _{The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going}
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
tsu2
Set up time, D0 – D20 valid to CLKOUT↓
th2
Hold time, CLKOUT↓ to D0 – D20 valid
tRSKM Receiver input skew margin§ (see Figure 7)
TEST CONDITIONS
CL = 8 pF,
See Figure 6
tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps¶,
MIN TYP† MAX UNIT
5
ns
5
ns
490
ps
td
Delay time, CLKIN↑ to CLKOUT↓
(see Figure 7)
tc = 15.38 ns (± 0.2%),
CL = 8 pF
3.7
ns
tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns,
See Figure 8
± 80
∆ tc(o) _{Cycle time, change in output clock period#}
tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
See Figure 8
ps
± 300
ten
Enable time, SHTDN↑ to Dn valid
See Figure 9
1
ms
tdis
Disable time, SHTDN↓ to off state
See Figure 10
400
ns
tt
Transition time, output (10% to 90% tr or tf)
CL = 8 pF
3
ns
tw
Pulse duration, output clock
0.43 tc
ns
† _{All typical values are at VCC = 3.3 V, TA = 25°C.}
* ń ^tc
§ _{The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by 14}
tsu1 th1
¶ _{|Input clock jitter| is the magnitude of the change in input clock period.}
# _{∆ tc(o) is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles.}
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