SN74ALS29841 Datasheet, PDF (5/6 Pages) Texas Instruments – 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALS29841
10-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS149A – JUNE 1988 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
Test Point
From Output
Under Test
CL
(see Note A)
R1
1 kΩ
VCC
S1
RL = 180 Ω
All Diodes
1N916 or 1N3064
S2
SWITCH POSITION TABLE
TEST
S1
S2
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
LOAD CIRCUIT
Timing Input
tsu
Data Input
3V
1.5 V
1.5 V
0
th
3V
1.5 V
0
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
High-Level
Pulse
Low-Level
Pulse
1.5 V
tw
1.5 V
3V
1.5 V
0
3V
1.5 V
0
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
3V
0
tPHL
VOH
1.5 V
VOL
tPLH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Control
tPZL
Waveform 1
(see Note B)
tPZH
Waveform 2
(see Note B)
1.5 V
1.5 V
tPHZ
1.5 V
tPLZ
3V
0
≈ 4.5 V
≈ 1.5 V
VOL
0.5 V
1.5 V
VOH
0.5 V
≈ 1.5 V
≈0
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
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