SN65MLVD201_07 Datasheet, PDF (5/26 Pages) Texas Instruments – MULTIPOINT-LVDS LINE DRIVER AND RECEIVER

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SN65MLVD201, SN65MLVD203
SN65MLVD206, SN65MLVD207
SLLS558C – DECEMBER 2002 – REVISED JANUARY 2007
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
I_A
I_B
I_AB
I_A(OFF)
I_B(OFF)
I_AB(OFF)
C_A
C_B
C_AB
C_A/B
PARAMETER
Receiver or transceiver with driver
disabled input current
Receiver or transceiver with driver
disabled input current
Receiver or transceiver with driver
disabled differential input current
(I_A – I_B)
Receiver or transceiver power-off
input current
Receiver or transceiver power-off
input current
Receiver input or transceiver
power-off differential input current
(I_A – I_B)
Transceiver with driver disabled input
capacitance
Transceiver with driver disabled input
capacitance
Transceiver with driver disabled
differential input capacitance
Transceiver with driver disabled input
capacitance balance, (C_A/C_B)
TEST CONDITIONS
V_A = 3.8 V,
V_A = 0 V or 2.4 V,
V_A = –1.4 V,
V_B = 3.8 V,
V_B = 0 V or 2.4 V,
V_B = –1.4 V,
V_B = 1.2 V,
V_B = 1.2 V
V_B = 1.2 V
V_A = 1.2 V
V_A = 1.2 V
V_A = 1.2 V
V_A = V_B,
1.4 ≤ V_A ≤ 3.8 V
V_A = 3.8 V,
V_A = 0 V or 2.4 V,
V_A = –1.4 V,
V_B = 3.8 V,
V_B = 0 V or 2.4 V,
V_B = –1.4 V,
V_B = 1.2 V,
V_B = 1.2 V,
V_B= 1.2 V,
V_A = 1.2 V,
V_A = 1.2 V,
V_A = 1.2 V,
0 V ≤ V_CC ≤ 1.5 V
0 V ≤ V_CC ≤ 1.5 V
0 V ≤ V_CC ≤ 1.5 V
0 V ≤ V_CC ≤ 1.5 V
0 V ≤ V_CC ≤ 1.5 V
0 V ≤ V_CC ≤ 1.5 V
V_A = V_B, 0 V ≤ V_CC ≤ 1.5 V, –1.4 ≤ V_A ≤ 3.8 V
V_A = 0.4 sin (30E6πt) + 0.5V⁽²⁾,
V_B = 0.4 sin (30E6πt) + 0.5 V⁽²⁾,
V_AB = 0.4 sin (30E6πt)V⁽²⁾
V_B = 1.2 V
V_A = 1.2 V
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
MIN TYP⁽¹⁾ MAX
0
32
–20
20
–32
0
0
32
–20
20
–32
0
-4
4
0
32
–20
20
–32
0
0
32
–20
20
–32
0
–4
4
5
5
3
0.99
1.01
UNIT
µA
µA
µA
µA
µA
µA
pF
pF
pF
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
t_PLH
t_PHL
t_r
t_f
t_sk(p)
t_sk(pp)
t_jit(per)
t_jit(pp)
t_PHZ
t_PLZ
t_PZH
t_PZL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t_PHL – t_PLH|)
Part-to-part skew⁽²⁾
Period jitter, rms (1 standard deviation)⁽³⁾
Peak-to-peak jitter^{(3) (5)}
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
See Figure 5
100 MHz clock input⁽⁴⁾
200 Mbps 2¹⁵–1 PRBS input⁽⁶⁾
See Figure 6
1
1.5 2.4 ns
1
1.5 2.4 ns
1
1.6 ns
1
1.6 ns
0 100 ps
1 ns
2
3 ps
30 130 ps
7 ns
7 ns
7 ns
7 ns
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) t_sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) t_r = t_f = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) Peak-to-peak jitter includes jitter due to pulse skew (t_sk(p)).
(6) t_r = t_f = 0.5 ns (10% to 90%), measured over 100 k samples.
Copyright © 2002–2007, Texas Instruments Incorporated
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