OMAP-L137_1 Datasheet, PDF (5/7 Pages) Texas Instruments – Low-Power Applications Processor Silicon Revision 1.0

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Non-Cached Mode
Advisory 1.0.1
Advisory 1.0.1 — ARM Data Cache in Write-Back Mode is Not Functional: Must Use Write-Through or
ARM Data Cache in Write-Back Mode is Not Functional: Must Use Write-Through
or Non-Cached Mode
Revision(s) Affected 1.0
Details
The ARM926 subsystem allows data memory regions to be write-back cachable,
write-through cachable, or non-cached. On this device revision, the Write-Back mode is
not functional; therefore, Write-Through or Non-Cached mode must always be used.
Workaround(s)
Only the Write-Through or Non-Cached mode can be used. Write-Through mode is
preferred for better performance. The cache operation is controlled using the C and B
bits in page or section descriptors. For operation in Write-Through mode, the C and B
bits (bits 3:2 in the descriptor) must be set to a value of 10b.
The following is example code using a section descriptor to create a table entry for the
first 1MB of external SDRAM on EMIFB as write-through cachable:
LDR r1, SDRAM0_ADDR
LDR r2, SDRAM0_DATA
STR r2, [r0, r1, LSL#2]
offset * 4
SDRAM0_ADDR
.word
SDRAM0_DATA
.word
; table offset for SDRAM0 region
; descriptor pattern for SDRAM0 region
; store the table entry at TTB base + table
0x00000C00
0xC0000CFA
For more information on ARM data cache modes and how to configure them, refer to the
ARM926EJ-S™ Technical Reference Manual available at www.arm.com/documentation.
Chapter 4 of the ARM926EJ-S™ Technical Reference Manual provides details about
cache operations on the ARM926EJ-S processor.
Section descriptor: A section descriptor provides the base address of a 1MB block of
memory. Figure 2 shows the format of a section descriptor.
31
20 19
12
11
10
9
8
5
4
3
2
1
0
section base address
AP
SBZ
AP
Domain
1
C
B
1
0
Figure 2. Section Descriptor
Table 2 shows the Section Descriptor bit assignments. Table 3 shows the Page Table C
and B bit settings for the DCache.
BITS
31:20
19:12
11:10
9
8:5
4
3:2
1:0
Table 2. Section Descriptor Bits
DESCRIPTION
Form the corresponding bits of the physical address for a section.
Always written as 0.
Specify the access permissions for this section.
Always written as 0.
Specify one of the 16 possible domains, held in the domain access control register, that
contain the primary access controls.
Should be written as 1, for backwards compatibility.
Indicate if the area of memory mapped by this section is treated as write-back cacheable,
write-through cacheable, noncached buffered, or noncached nonbuffered.
These bits must be 10 to indicate a section descriptor
SPRZ291 – October 2008
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OMAP-L137
5
Silicon Revision 1.0