MSP430G2X52 Datasheet, PDF (5/58 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430G2x52
MSP430G2x12
www.ti.com
SLAS722B – DECEMBER 2010 – REVISED MARCH 2011
TERMINAL
NAME
14
PW
P1.0/
TA0CLK/
ACLK/
2
A0/
CA0
P1.1/
TA0.0/
3
A1/
CA1
P1.2/
TA0.1/
4
A2/
CA2
P1.3/
ADC10CLK/
CAOUT/
5
A3/
VREF-/VEREF/
CA3
P1.4/
SMCLK/
TA0.2/
A4/
6
VREF+/VEREF+/
CA4/
TCK
P1.5/
TA0.0/
SCLK/
7
A5/
CA5/
TMS
P1.6/
TA0.1/
SDO/
SCL/
8
A6/
CA6/
TDI/TCLK
NO.
16
RSA
1
2
3
4
5
6
7
20
N, PW
2
3
4
5
6
7
14
Table 2. Terminal Functions
I/O
DESCRIPTION
General-purpose digital I/O pin
Timer0_A, clock signal TACLK input
I/O ACLK signal output
ADC10 analog input A0⁽¹⁾
Comparator_A+, CA0 input
General-purpose digital I/O pin
Timer0_A, capture: CCI0A input, compare: Out0 output
I/O _{ADC10 analog input A1(1)}
Comparator_A+, CA1 input
General-purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare: Out1 output
I/O _{ADC10 analog input A2(1)}
Comparator_A+, CA2 input
General-purpose digital I/O pin
ADC10, conversion clock output⁽¹⁾
Comparator_A+, output
I/O _{ADC10 analog input A3(1)}
ADC10 negative reference voltage⁽¹⁾
Comparator_A+, CA3 input
General-purpose digital I/O pin
SMCLK signal output
Timer0_A, capture: CCI2A input, compare: Out2 output
I/O ADC10 analog input A4⁽¹⁾
ADC10 positive reference voltage⁽¹⁾
Comparator_A+, CA4 input
JTAG test clock, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out0 output
USI: clk input in I2C mode; clk in/output in SPI mode
I/O _{ADC10 analog input A5(1)}
Comparator_A+, CA5 input
JTAG test mode select, input terminal for device programming and test
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
USI: Data output in SPI mode
I/O USI: I2C clock in I2C mode
ADC10 analog input A6⁽¹⁾
Comparator_A+, CA6 input
JTAG test data input or test clock input during programming and test
(1) Available only on MSP430G2x52 devices.
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