M38510 Datasheet, PDF (5/21 Pages) Texas Instruments – LF198JAN Monolithic Sample-and-Hold Circuits

LF198JAN
www.ti.com
SNOSAJ2A – FEBRUARY 2005 – REVISED MARCH 2013
Electrical Characteristics DC Parameters (continued)
Symbol
Parameter
Conditions
I_CH+
I_CH-
V_Th(H)
V_Th(L)
I_HL+
I_HL-
Z_O
V_HS
Hold Capacitor Charge Current
Hold Capacitor Charge Current
Differential Logic Threshold
Differential Logic Threshold
Hold Mode Leakage Current
Hold Mode Leakage Current
Output Impedance
(HOLD) Step Voltage
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V
Logic = 2.0V, Logic Ref = 2.0V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V
Logic = 0.8V, Logic Ref = 2.0V
+V_CC = 3.5V, -V_CC = -26.5V,
V_CM = -11.5V
+V_CC = 26.5V, -V_CC = -3.5V, V_CM
= 11.5V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V
+V_CC = 3.5V, -V_CC = -26.5V, V_CM
= 11.5V
+V_CC = 26.5V, -V_CC = -3.5V, V_CM
= -11.5V
F_RR
Feedthrough Rejection Ratio
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V, V_I = 0V to 11.5V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V, V_I = 11.5V to 0V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V, V_I = 0V to -11.5V
+V_CC = 15V, -V_CC = -15V,
V_CM = 0V, V_I = -11.5V to 0V
Notes
Min Max
-3.0
-2.0
3.0
2.0
1.0
-10 10
See ⁽¹⁾
See ⁽¹⁾
See ⁽²⁾
See ⁽²⁾
-0.100
-50
-0.100
-50
0.100
50
0.100
50
2.0
-2.0 2.0
-5.0 5.0
-2.0 2.0
-5.0 5.0
86
80
86
80
86
80
86
80
Unit
mA
mA
mA
mA
mA
µA
nA
nA
nA
nA
Ω
mV
mV
mV
mV
dB
dB
dB
dB
dB
dB
dB
dB
Sub-
groups
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1
2
1
2
1, 2, 3
1
2, 3
1
2, 3
1
2, 3
1
2, 3
1
2, 3
1
2, 3
(1) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or
elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is ensured over full
input signal range.
(2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
additional 0.5 mV step with a 5V logic swing and a 0.01μF hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
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