DAC5686_15 Datasheet, PDF (5/53 Pages) Texas Instruments – 16-BIT, 500-MSPS, 2×–16× INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER

DAC5686
www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009
DEVICE INFORMATION
TERMINAL
NAME
NO.
AGND
1, 4, 7, 9,
12, 17, 19,
22, 25
AVDD
2, 3, 8, 10,
14, 16, 18,
23, 24
BIASJ
13
CLK1
59
CLK1C
60
CLK2
62
CLK2C
63
CLKGND
58, 64
CLKVDD
61
DA[15:0]
34–36,
39–43,
48–55
DB[15:0]
92–90,
87–83,
78–71
DGND
DVDD
EXTIO
27, 38, 45,
57, 69, 81,
88, 93, 99
26, 32, 37,
44, 56, 68,
82, 89, 100
11
EXTLO
IOUTA1
IOUTA2
IOUTB1
IOUTB2
IOGND
IOVDD
LPF
PHSTR
15
21
20
5
6
47, 79
46, 80
66
94
PLLGND
65
PLLVDD
67
PLLLOCK 70
QFLAG
98
RESETB
95
SCLK
29
SDENB
28
Terminal Functions
I/O
I Analog ground return
DESCRIPTION
I Analog supply voltage
I/O Full-scale output current bias
I External clock input; data clock input
I Complementary external clock input; data clock input
I External clock input; sample clock for the DAC (optional if PLL disabled)
I Complementary external clock input; sample clock for the DAC (optional if PLL disabled)
Ground return for internal clock buffer
Internal clock buffer supply voltage
I A-channel data bits 0 through 15
DA15 is most significant data bit (MSB).
DA0 is least significant data bit (LSB). Internal pulldown
I B-channel data bits 0 through 15
DB15 is most significant data bit (MSB).
DB0 is least significant data bit (LSB). Internal pulldown
Note: The order of the B data bus can be reversed by register rev_bbus.
Digital ground return
Digital supply voltage
I Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to
AGND when used as reference output
I Internal reference ground. Connect to AVDD to disable the internal reference
O A-channel DAC current output. Full scale when all input bits are set to 1
O A-channel DAC complementary current output. Full scale when all input bits are set to 0
O B-channel DAC current output. Full scale when all input bits are set to 1
O B-channel DAC complementary current output. Full scale when all input bits are set to 0
Digital I/O ground return
Digital I/O supply voltage
I/O PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).
I The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets
the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition
sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO
phase accumulator. Internal pulldown
Ground return for internal PLL
PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.
O PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In
external clock mode, PLLLOCK outputs the input rate clock.
I Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an
input to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can
be left open when not used. Internal pulldown
I Resets the chip when low. Internal pullup
I Serial interface clock. Internal pulldown
I Active-low serial data enable, always an input to the DAC5686. Internal pulldown
Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5686
Submit Documentation Feedback
5