CDCFR83 Datasheet, PDF (5/12 Pages) Texas Instruments – DIRECT RAMBUS CLOCK GENERATOR

CDCFR83
DIRECT RAMBUS CLOCK GENERATOR
recommended operating conditions
Supply voltage, VDD
High-level input voltage, VIH (CMOS)
Low-level input voltage, VIL (CMOS)
Initial phase error at phase detector inputs (required range for phase aligner)
REFCLK low-level input voltage, VIL
REFCLK high-level input voltage, VIH
Input signal low voltage, VIL (STOPB)
Input signal high voltage, VIH (STOPB)
Input reference voltage for (REFCLK) (VDDIR)
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
SCAS665A – APRIL 2001 REVISED MARCH 2002
MIN
3.135
0.7 × VDD
NOM
3.3
– 0.5 × tc(PD)
0.7 × VDDIR
0.7 × VDDIPD
1.235
1.235
–40
MAX
3.465
0.3 × VDD
0.5 × tc(PD)
0.3 × VDDIR
0.3 × VDDIPD
3.465
3.465
–16
16
85
UNIT
V
V
V
V
V
V
V
V
V
mA
mA
°C
timing requirements
Input cycle time, tc(in)
Input cycle-to-cycle jitter
Input duty cycle over 10,000 cycles
Input frequency modulation, fmod
Modulation index, nonlinear maximum 0.5%
Phase detector input cycle time (PCLKM and SYNCLKN)
Input slew rate, SR
Input duty cycle (PCLKM and SYNCLKN)
MIN
10
40%
30
30
1
25%
MAX
40
250
60%
33
0.6%
100
4
75%
UNIT
ns
ps
kHz
ns
V/ns
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