CDC391 Datasheet, PDF (5/7 Pages) Texas Instruments – 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

From Output
Under Test
CL = 50 pF
(see Note A)
CDC391
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
SCAS334A – DECEMBER 1992 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
7V
S1
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
Input
tPLH
Output
1.5 V
3V
1.5 V
0V
tPHL
2V
0.8 V
2V
1.5 V
VOH
0.8 V _VOL
tr
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
3V
Control
(low-level
enabling)
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPHZ
1.5 V
3.5 V
VOL + 0.3 V
VOL
VOH
VOH – 0.3 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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