CDC2586 Datasheet, PDF (5/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC2586
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998
Terminal Functions
TERMINAL
NAME
NO.
CLKIN
45
CLR
40
FBIN
48
OE
42
SEL1, SEL0 51, 50
TEST
41
1Y1 – 1Y3
2Y1 – 2Y3
3Y1 – 3Y3
2, 5, 8
12, 15, 18
22, 25, 28
4Y1 – 4Y3 32, 35, 38
I/O
DESCRIPTION
Clock input. CLKIN is the clock signal to be distributed by the CDC2586 clock-driver circuit. CLKIN provides
the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed
I frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLKIN
signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference
signal.
I CLR is used for testing purposes only.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
I the twelve clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks
to obtain zero phase delay between FBIN and CLKIN.
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly
I from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,
when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before
the PLL obtains phase lock.
I
Output configuration select. SEL0 and SEL1 select the output configuration for each output bank (e.g., 1/2×,
1×, or 2×) (see Tables 1 and 2).
TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs
I operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be strapped to GND for normal operation.
Output ports. These outputs are configured by the select inputs (SEL1, SEL0) to transmit one-half or
one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output
O
frequency is dependent on the select inputs and the frequency of the output being fed back to FBIN
(see Tables 1 and 2). The duty cycle of the Y output signals is nominally 50%, independent of the duty cycle
of CLKIN. Each output has an internal series resistor to dampen transmission-line effects and improve the
signal integrity at the load.
Output ports. 4Y1 – 4Y3 transmit one-half the frequency of the VCO regardless of the state of the select
inputs. The relationship between the CLKIN frequency and the output frequency is dependent on the
O frequency of the output being fed back to FBIN (see Tables 1 and 2). The duty cycle of the Y output signals
is nominally 50%, independent of the duty cycle of CLKIN. Each output has an internal series resistor to
dampen transmission-line effects and improve the signal integrity at the load.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, V_O (see Note 1) . . . – 0.5 V to 5.5 V
Current into any output in the low state, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at T_A = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
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