CD74HC4543 Datasheet, PDF (5/10 Pages) Texas Instruments – High-Speed CMOS Logic BCD to 7-Segment Latch/Decoder/Driver for LCDs

CD74HC4543
Prerequisite for Switching Specifications
PARAMETER
Setup Time Dn to LD
Hold Time Dn to LD
Latch Disable Pulse
Width
SYMBOL V_CC (V) MIN
t_SU
2
60
4.5
12
6
10
t_H
2
30
4.5
6
6
5
t_W
2
50
4.5
10
6
9
25^oC
TYP
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-40^oC TO 85^oC
MIN TYP MAX
75
-
-
15
-
-
13
-
-
40
-
-
8
-
-
7
-
-
65
-
-
13
-
-
11
-
-
-55^oC TO 125^oC
MIN TYP MAX UNITS
90
-
-
ns
18
-
-
ns
15
-
-
ns
45
-
-
ns
9
-
-
ns
8
-
-
ns
75
-
-
ns
15
-
-
ns
13
-
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Propagation Delay,
Dn to Output
t_PLH, t_PHL C_L = 50pF
2
-
- 340
-
425
-
510
ns
4.5 -
-
68
-
85
-
102
ns
6
-
- 58
-
72
-
87
ns
Propagation Delay,
LD to Output
C_L = 15pF
5
- 28 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
2
-
- 370
-
465
-
555
ns
4.5 -
-
74
-
93
-
111
ns
6
-
- 63
-
79
-
94
ns
Propagation Delay,
BI to Output
C_L = 15pF
5
- 31 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
2
-
- 265
-
330
-
400
ns
4.5 -
-
53
-
66
-
80
ns
6
-
- 45
-
56
-
68
ns
Propagation Delay,
PH to Output
C_L = 15pF
5
- 22 -
-
-
-
-
ns
t_PLH, t_PHL C_L = 50pF
2
-
- 200
-
250
-
300
ns
4.5 -
-
40
-
50
-
60
ns
6
-
- 34
-
43
-
51
ns
Transition Time
C_L = 15pF
5
- 17 -
-
-
-
-
ns
t_THL, t_TLH C_L = 50pF
2
-
- 250
-
315
-
375
ns
4.5 -
-
50
-
63
-
75
ns
6
-
- 43
-
54
-
64
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_I
C_PD
-
-
-
-
10
-
10
-
10
pF
-
5
- 52 -
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per package.
4. P_D = C_PD V_CC2 f_i + Σ C_L V_CC2 f_o where f_i = input frequency, f_o = output frequency, C_L = output load capacitance, V_CC = supply voltage.
5