CD74HC195 Datasheet, PDF (5/6 Pages) Texas Instruments – High Speed CMOS Logic 4-Bit Parallel Access Register

CD74HC195
Test Circuit and Waveforms
t_r
t_f
CLOCK _VS
Q OR Q
90%
10%
t_W
l/f_MAX
t_PLH t_PHL
90%
10%
t_TLH t_THL
V_CC
GND
0.5 V_CC
FIGURE 1. CLOCK PRE-REQUISITE AND PROPAGATION
DELAYS AND OUTPUT TRANSITION TIMES
RESET
Q
t_PHL
Q
CLOCK
t_W
V_S
t_PLH
0.5 V_CC
V_S
t_REM
0.5 V_CC
V_CC
GND
V_CC
GND
FIGURE 2. MASTER RESET PRE-REQUISITE AND
PROPAGATION DELAYS
VALID
PE, K
V_S
J
t_SU
t_h
CLOCK
0.5 V_CC
V_CC
GND
GND
FIGURE 3. J, K OR PARALLEL ENABLE PRE-REQUISITE TIMES
5