CD74HC14PWRG4 Datasheet, PDF (5/16 Pages) Texas Instruments – High-Speed CMOS Logic Hex Inverting Schmitt Trigger

Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay,
A to Y
Output Transition Times
t_PLH, t_PHL C_L = 50pF
C_L = 50pF
C_L = 15pF
C_L = 50pF
t_TLH, t_THL C_L = 50pF
2
-
- 135
-
4.5 -
-
27
-
5
- 11 -
-
6
-
- 23
-
2
-
- 75
-
4.5 -
-
15
-
170
-
205
ns
34
-
41
ns
-
-
-
ns
29
-
35
ns
95
18
110
ns
19
-
22
ns
6
-
- 13
-
16
-
19
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
C_I
C_PD
-
-
-
-
10
-
10
-
10
pF
-
5
- 20 -
-
-
-
-
pF
HCT TYPES
Propagation Delay,
A to Y
t_PLH, t_PHL C_L = 50pF
4.5 -
-
38
-
48
-
57
ns
C_L = 15pF
5
- 16 -
-
-
-
-
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5 -
-
15
-
19
-
22
ns
Input Capacitance
C_I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C_PD
-
5
- 20 -
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per inverter.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = input frequency, C_L = output load capacitance, V_CC = supply voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5