CD74FCT543 Datasheet, PDF (5/6 Pages) Texas Instruments – BiCMOS FCT Interface Logic, Octal Register/Transceiver, Three-State

CD74FCT543
Test Circuits and Waveforms
t_r, t_f = 2.5ns
(NOTE 8) ^VI
3V
0
PULSE Z_O
GEN
R_T = Z_O
R_T
V_CC
V₀
DUT
C_L
50pF
7V
500Ω
R_L
500Ω
R_L
NOTE:
8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z_OUT ≤ 50Ω;
t_f, t_r ≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
SWITCH POSITION
TEST
SWITCH
t_PLZ, t_PZL, Open Drain
Closed
t_PHZ, t_PZH, t_PLH, t_PHL
Open
DEFINITIONS:
C_L = Load capacitance, includes jig and probe
capacitance.
R_T = Termination resistance, should be equal to Z_OUT of
the Pulse Generator.
V_IN = 0V to 3V.
Input: t_r = t_f = 2.5ns (10% to 90%), unless otherwise specified
DATA
INPUT
t_SH
t_H
TIMING
INPUT
ASYNCHRONOUS CONTROL
t_REM
SYNCHRONOUS CONTROL
PRESET CLEAR
CLOCK ENABLE
ETC.
t_SH
t_H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
LOW-HIGH-LOW
PULSE
1.5V
t_W
HIGH-LOW-HIGH
PULSE
1.5V
FIGURE 3. PULSE WIDTH
ENABLE
DISABLE
CONTROL INPUT
OUTPUT
NORMALLY LOW
t_PZL
SWITCH
CLOSED
t_PZH
OUTPUT SWITCH
NORMALLY HIGH OPEN
t_PLZ
3.5V
1.5V
t_PHZ
1.5V
0V
3V
1.5V
0V
3.5V
0.3V _VOL
0.3V ^VOH
0V
FIGURE 4. ENABLE AND DISABLE TIMING
SAME PHASE
INPUT TRANSITION
t_PLH
t_PHL
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t_PLH
t_PHL
FIGURE 5. PROPAGATION DELAY
3V
1.5V
0V
V_OH
1.5V
V_OL
3V
1.5V
0V
OTHER
OUTPUTS
OUTPUT
UNDER
TEST
V_OH
V_OL
V_OH
V_OHV
V_OLP
V_OL
NOTES:
9. V_OLP is measured with respect to a ground reference near the output under test. V_OHV is measured with respect to V_OH.
10. Input pulses have the following characteristics:
P_RR ≤ 1MHz, t_r = 2.5ns, t_f = 2.5ns, skew 1ns.
11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
8-5