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CD54HC85_08 Datasheet, PDF (5/18 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Magnitude Comparator
◁
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85
Switching Specifications Input tr, tf = 6ns (Continued)
TEST
25oC
PARAMETER
SYMBOL CONDITIONS VCC (V) MIN TYP MAX
(A > B) IN, (A < B) IN, (A = B) IN tPLH, tPHL CL = 50pF
to (A > B) OUT, (A < B) OUT
2
-
- 140
4.5
-
-
28
-40oC TO
85oC
MIN MAX
-
175
-
35
-55oC TO
125oC
MIN MAX
-
210
-
42
(A > B) IN to (A = B) OUT
CL = 15pF
CL = 50pF
tPLH, tPHL CL = 50pF
5
-
11
-
-
-
-
-
6
-
-
24
-
30
-
36
2
-
-
120
-
150
-
180
4.5
-
-
24
-
30
-
36
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL = 15pF
CL = 50pF
-
5
-
9
-
-
-
-
-
6
-
-
20
-
26
-
31
5
-
24
-
-
-
-
-
Output Transition Times
(Figure 1)
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
4.5
-
-
15
-
19
-
22
6
-
-
13
-
16
-
19
Input Capacitance
HCT TYPES
Propagation Delay,
An, Bn to (A > B) OUT,
(A < B) OUT
CIN -
tPLH, tPHL CL = 50pF
CL = 15pF
-
-
-
10
-
10
-
10
4.5
-
-
37
-
46
-
56
5
-
15
-
-
-
-
-
An, Bn to (A = B) OUT
(A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
(A > B) IN to (A = B) OUT
Output Transition Times
(Figure 1)
tPLH, tPHL CL = 50pF
CL = 15pF
tPLH, tPHL CL = 50pF
CL = 15pF
tPLH, tPHL CL = 50pF
CL = 15pF
tTLH, tTHL CL = 50pF
4.5
-
-
40
-
50
-
60
5
-
17
-
-
-
-
-
4.5
-
-
30
-
38
-
45
5
-
12
-
-
-
-
-
4.5
-
-
31
-
39
-
47
5
-
13
-
-
-
-
-
4.5
-
-
15
-
19
-
22
Power Dissipation Capacitance CPD -
(Notes 3, 4)
5
-
26
-
-
-
-
-
Input Capacitance
NOTES:
CIN
-
-
-
-
10
-
10
-
10
3. CPD is used to determine the dynamic power consumption, per gate/package.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tr = 6ns
INPUT
2.7V
1.3V
0.3V
tf = 6ns
3V
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
1.3V
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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