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CD54HC4017_08 Datasheet, PDF (5/16 Pages) Texas Instruments – High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
◁
CD54HC4017, CD74HC4017
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO
85oC
-55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
MR to any Dec. Out
tPLH,
CL = 50pF
2
-
- 230 - 290
-
345
ns
tPHL
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
MR to TC
tPLH,
CL = 50pF
2
-
- 230 - 290
-
345
ns
tPHL
CL = 50pF
4.5
-
-
46
-
58
-
69
ns
CL = 15pF
5
-
19
-
-
-
-
-
ns
CL = 50pF
6
-
-
39
-
49
-
59
ns
Transition Time TC, Dec. Out tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
6
-
-
13
-
16
-
19
ns
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum CP Frequency
fMAX
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation Capacitance
CPD
CL = 15pF
5
-
39
-
-
-
-
-
pF
(Notes 2, 3)
NOTES:
2. CPD is used to determine the dynamic power consumption, per package.
3. PD = VCC2 fi Σ€ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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