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CD54HC283_08 Datasheet, PDF (5/14 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry
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CD54HC283, CD74HC283, CD54HCT283, CD74HCT283
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
Input Capacitance
Power Dissipation
Capacitance, (Notes 3, 4)
TEST
25oC
SYMBOL CONDITIONS VCC (V) MIN TYP MAX
CIN
-
-
-
-
10
CPD
-
5
-
82
-
-40oC TO
85oC
MIN MAX
-
10
-
-
-55oC TO
125oC
MIN MAX
-
10
-
-
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
UNITS
pF
pF
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
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