CD54HC125 Datasheet, PDF (5/11 Pages) Texas Instruments – High-Speed CMOS Logic Quad Buffer, Three-State

CD54HC125, CD74HC125, CD54HCT125, CD74HCT125
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay Time
nA to nY
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
100
125
-
20
25
150
ns
30
ns
C_L = 15pF
5
8
-
-
CL = 50pF
6
-
17
21
-
ns
26
ns
Enable Delay Time
t_PZL, t_PZH C_L = 50pF
2
-
125
155
4.5
-
25
31
190
ns
38
ns
C_L = 15pF
5
10
-
-
CL = 50pF
6
-
21
26
-
ns
32
ns
Disable Delay Time
t_PLZ, t_PHZ CL = 50pF
2
-
125
155
C_L = 50pF
4.5
-
25
31
C_L = 15pF
5
10
-
-
CL = 50pF
6
-
21
26
190
ns
38
ns
-
ns
32
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
2
-
60
75
4.5
-
12
15
90
ns
18
ns
6
-
10
13
15
ns
Input Capacitance
Three-State Output
Capacitance
C_I
-
-
-
10
10
C_O
-
-
-
20
20
10
pF
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
29
-
-
-
pF
HCT TYPES
Propagation Delay Time
t_PLH, t_PHL C_L = 50pF
4.5
-
25
31
nA to nY
C_L = 15pF
5
10
-
-
Output Enable Time
t_PZL, t_PZH C_L = 50pF
4.5
-
25
31
C_L = 15pF
5
10
-
-
Output Disabling Time
t_PLZ, t_PHZ C_L = 50pF
4.5
-
28
35
C_L = 15pF
5
11
-
-
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5
-
12
15
Input Capacitance
C_I
-
-
-
10
10
Three-State Output
Capacitance
C_O
-
-
-
20
20
38
ns
-
ns
38
ns
-
ns
42
ns
-
ns
18
ns
10
pF
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
34
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per channel.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
5