CD54ACT163 Datasheet, PDF (5/10 Pages) Texas Instruments – CD54ACT161 CD74ACT161

CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
SCHS300 – APRIL 2000
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Data
Outputs
QA
QB
QC
QD
RCO
12 13 14 15 0 1 2
Count
Sync Preset
Clear
Inhibit
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